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general description the max5167 contains 32 sample-and-hold amplifiersdriven by a single multiplexed input. the control logic addressing the outputs is a simple 5-wire input to the multiplexer. additional logic allows two devices to function as a single 64-channel unit. clamping diodes on each output allows clamping between two external reference voltages. the max5167 is available with an output impedance of 50 , 500 , or 1k . the max5167 operates with +10v and -5v supplies,and a separate +5v digital logic supply. manufactured with a proprietary bicmos process, it provides high accuracy, fast acquisition time, low droop rate, and a low hold step. the max5167 has a typical linearity error of less than 0.01% and can accurately acquire an 8v step input signal to 0.01% accuracy in 2.5? within the +7v to -4v input signal range. transitions from sample mode to hold mode result in only a 0.5mv error. while in hold mode, the output voltage slowly droops at a rate of 1mv/s. the max5167 is available in a 48-pin tqfp package and is specified for both the commercial (0? to +70?) and extended-industrial (-40? to +85?) temperature ranges. ________________________applications automatic test systems (ate)industrial process controls arbitrary function generators avionics equipment features ? 32-channel sample/hold ? output clamps on each channel ? 0.01% accuracy of acquired signal ? 0.01% linearity error ? fast acquisition time: 2.5s ? low droop rate: 1mv/s ? low hold step: 0.25mv ? wide output voltage range: +7v to -4v max5167 32-channel sample/hold amplifier with output clamping diodes ________________________________________________________________ maxim integrated products 1 out21out20 out19 out18 out17 out16 v dd out15out14 out13 out12 out11 addr2addr3 addr4 select s/h config v l dgnd v ss agnd in ch 12 3 4 5 6 7 8 9 1011 12 1314 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 3635 34 33 32 31 30 29 28 27 26 25 cl out0out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 addr1addr0 out31 out30 out29 out28 out27 out26 out25 out24 out23 out22 tqfp max5167 top view pin configuration 19-1675; rev 0; 4/00 ordering information 48 tqfp pin- package temp. range 0? to +70? max5167lccm part 48 tqfp 0? to +70? max5167mccm 48 tqfp 0? to +70? MAX5167NCCM 48 tqfp -40? to +85? max5167lecm 48 tqfp -40? to +85? max5167mecm 48 tqfp -40? to +85? max5167necm 50 r out ( ) 500 1k 50 500 1k for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.for small orders, phone 1-800-835-8769. downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = +10.0v, v ss = -5.0v, v l = +5.0v ?%, agnd = dgnd = 0, r l = 5k , c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd.......................................................-0.3v to +11.0v v ss to agnd .........................................................-6.0v to +0.3v v dd to v ss ......................................................................+15.75v v l to dgnd ...........................................................-0.3v to +6.0v v l to agnd ...........................................................-0.3v to +6.0v dgnd to agnd.....................................................-0.3v to +2.0v in, out_ ....................................................................v ss to v dd logic inputs to dgnd ...........................................-0.3v to +6.0v c h , c l to agnd ..................................................-6.0v to +11.0v maximum current into c l and c h .................................. 80ma maximum current into out_............................................. 10ma maximum current into logic inputs ................................ 20ma continuous power dissipation (t a = +70?) 48-pin tqfp (derate 12.5mw/? above +70?)........1000mw operating temperature ranges max5167_ccm ..................................................0? to +70? max5167_ecm................................................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? figure 2 (note1) in = agnd to ?mv of final value figure 2 (note1) 100mv step to ?mv,r l = , figure 2 -4.0v < vin < +7v rl = 8v step to 0.08%,r l = , figure 2 r l = , c l = 250pf (note 1) v in = 0, sample mode v in = 0, sample mode 8v step with 500nsrising edge (note 1) max5167n in = agnd in = agnd +15? t a +65? (note 1) t a = +25? rl = t a = +25? conditions ns 200 t ap aperture delay ? 12 t h hold mode settling time 1 ? 2.5 4 t aq acquisition time v v ss v dd v cl output clamp low v v ss v dd v ch output clamp high ma 2 i sink output sink current ma 2 i source output source current 700 1000 1300 350 500 650 r out_ mv 0.25 1.00 v hs hold step % 0.01 0.08 linearity error 35 50 65 dc output impedance pf 10 20 c in input capacitance max5167m -72 -76 max5167l db -72 -76 analog crosstalk mv/s 14 0 droop rate mv -30 -5 +30 v os offset voltage ?/? 20 40 c l = 250pf for max5167l c l = 10nf for max5167m/67n v v ss +v dd - 0.75 2.4 v out_ output voltage range units min typ max symbol parameter t a = +25? t a = +25? analog section timing performance downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = +10.0v, v ss = -5.0v, v l = +5.0v ?%, agnd = dgnd = 0, r l = 5k , c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) note 1: guaranteed by design. note 2: do not exceed the absolute maximum rating for v dd to v ss of +15.75v (see absolute maximum ratings ). figure 2 (note1) figure 2 (note1) conditions ns 50 t ds data setup time ns 200 t pw s /h pulse width addr_ = +0.8v or +2.0v, s/ h = +0.8v or +2.0v ma 5 units min typ max symbol parameter r l = r l = (note 2) (note 2) in = dgnd or v cc figure 2 (note1) ma 36 i ss negative analog supply current ma 36 i dd positive analog supply current v 4.75 5 5.25 v l digital logic supply v -4.75 -5 -5.45 v ss negative analog supply v 9.5 10 10.5 v dd positive analog supply ? -1 +1 i i input current v 0.8 v il input voltage low v 2.0 v ih input voltage high ns 150 t dh data hold time for v dd and v ss , sample mode, in = agnd addr_ = dgnd or v l , s/ h = dgnd or v l db -60 -75 psrr power-supply rejection ratio ma 0.5 i l digital logic supply current power supplies digital inputs downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes 4 _______________________________________________________________________________________ typical operating characteristics (v dd = +10v, v ss = -5v, v l = +5v, v in = +5v, r l = , c l = 0, agnd = dgnd = 0, v ch = v dd , v cl = v ss , t a = +25?, unless otherwise noted.) 0 0.40.2 1.00.8 0.6 1.2 1.4 1.81.6 2.0 -4 -2 -1 -3 01234567 droop rate vs. input voltage max5167 toc 01 input voltage (v) droop rate (mv/s) 0 10 3020 40 50 -40 10 -15 35 60 85 droop rate vs. temperature max5167 toc 02 temperature (?) droop rate (mv/s) 0 -40-20 -80-60 -100 -120 0.1 10 1 100 1000 10,000 psrr sample mode max5167 toc 03 frequency (khz) psrr (db) negative supply (v ss ) positive supply (v dd ) 0 -40-20 -80-60 -100 -120 0.1 10 1 100 1000 10,000 psrr hold mode max5167 toc 04 frequency (khz) psrr (db) negative supply (v ss ) positive supply (v dd ) 0 -20 -140 -60-40 -80 -100 -120 -160 -4 -2 -1 0 -3 1 2 5 46 37 hold step vs. input voltage max5167 toc 05 input voltage (v) hold step ( v) 80 9085 100 95 115110 105 120 -55 -15 -35 5 25 45 65 85 hold step vs. temperature max5167 toc 06 temperature ( c) hold step ( v) -5.0 -4.6-4.8 -4.2-4.4 -3.8 -3.6 -3.4 -3.2-4.0 -3.0 -4 -2 -3 -1 0 1 2 3 4 5 6 7 offset voltage vs. input voltage max5167 toc 07 input voltage (v) offset voltage (mv) -7 -5-6 -2-3 -4 -1 0 -40 -15 10 35 60 85 offset voltage vs. temperature max5167 toc 08 temperature ( c) offset voltage (mv) downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes _______________________________________________________________________________________ 5 name function 1 addr2 bit 2 of the address decoder 2 addr3 bit 3 of the address decoder pin 3 addr4 bit 4 of the address decoder 4 select enables the s /h pin. the polarity of select is determined by the state of the config pin. if config is low, then select is active-high. if config is high, then select is active-low. when select is notin its active state, all 32 channels are in hold mode independent of the s /h pin. 8 dgnd digital gnd 7 v l +5v logic supply 6 config sets the polarity of the select pin. 5 s /h puts the selected channel into sample mode when low. places all channels into hold mode when high. 13 cl clamp low pin 12 ch clamp high pin 11 in input pin 10 agnd analog gnd 9 v ss -5v analog supply pin description 47 addr0 bit 0 of the address decoder 31?6 out16?ut31 output 16?1 pin 30 v dd +10v analog supply 14?9 out0?ut15 output 0?5 pin 48 addr1 bit 1 of the address decoder downloaded from: http:///
max5167 detailed description digital interface the max5167 has three logic control inputs and fiveaddress lines. the address lines are inputs to a demul- tiplexer that selects one of the 32 outputs in a standard addressing scheme ( table 1 ). the analog input is con- nected to the addressed sample/hold when directed by the control logic ( table 2 ). the three logic control lines determine the state of theaddressed sample/hold. the normal circuit connection for this device is to hardwire config and select to opposing logic voltages. when select and config are in opposite states (one high and the other low), the five address lines select one of the sample/holds. use the s /h line to place the selected channel into sample or hold mode. the other 31 channels will remain in holdmode. if an active-high sampling mode is desired, tie s /h and config low. in this case, select controls theaddressed channel with a high state putting that chan- nel into sample mode. the select and config pins allow the design of avirtual 64-channel device using two of the max5167s. see the applications information section for more infor- mation about the 64 output addressing scheme. sample/hold the max5167 contains 32 buffered sample/hold circuitswith internal hold capacitors. internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. the value of the hold capacitor affects acquisition time and droop rate. smaller capacitance allows faster acquisition times but increases the droop rate. larger values increase hold acquisition time. the hold capacitor used in the max5167 provides fast 2.5? (typ) acquisition time while maintaining a relatively low 1mv/s (typ) droop rate, mak- ing the sample/hold ideal for high-speed sampling. sample mode when select and config are in opposing logic states,the s /h line controls the mode of operation. sample mode is entered when s /h is low. during sample mode, the selected multiplexer channel connects to in, allowing the 32-channel sample/hold amplifier with output clamping diodes 6 _______________________________________________________________________________________ max5167 sw1 cs sw2 sw30 sw31 addr0 addr4 s/h select config in out0 out1 out30 out31 ch cl figure 1. functional diagram downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes _______________________________________________________________________________________ 7 table 1. channel/output selection table 2. logic table for config, select, and s /h 0 1 0 1 x select sampling 1 0 sampling 0 hold 0 0 0 hold 1 0 hold x 1 channel function config s /h (sample/hold) 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 output addr0 addr3 addr4 addr2 addr1 1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 vout12 is selected vout11 is selected vout10 is selected vout19 is selected vout18 is selected vout17 is selected vout13 is selected vout14 is selected vout15 is selected vout2 is selected vout1 is selected vout0 is selected vout16 is selected vout9 is selected vout8 is selected vout7 is selected vout3 is selected vout4 is selected vout5 is selected vout6 is selected vout26 is selected vout25 is selected vout24 is selected vout31 is selected vout27 is selected vout28 is selected vout29 is selected vout30 is selected vout23 is selected vout22 is selected vout21 is selected vout20 is selected downloaded from: http:///
max5167 hold capacitor to acquire the input signal. to guaranteean accurate sample, maintain sample mode for at least 4?. the output of the sample/hold amplifier tracks the input after 4?. only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. hold mode no matter what the condition of the other control lines,s /h = high places the max5167 into an all-channel hold mode. hold mode disables the multiplexer anddisconnects all 32 sample/holds from the input. when a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a 1mv/s typical droop rate (towards v dd ). hold step when switching between sample mode and hold mode,the voltage of the hold capacitor changes due to charge injection from stray capacitance. this voltage change, called hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. the max5167 limits the hold step to 0.25mv (typ). an output capacitor to ground can be used to filter out this small hold-step error. output the max5167 contains an output buffer for each multi-plexer channel (32 total), so the hold capacitor sees a high-impedance input that reduces the droop rate. the capacitor droops at 1mv/s (typ) while in hold mode. the buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output ( figure 1 ) for selected output filtering. to provide greater design flexibility, the max5167 is avail-able with an output impedance of 50 , 500 , or 1k . output loads increase the analog supply current (i dd and i ss ). excessive loading of the output(s) drastically increases power dissipation. do not exceed the maximumpower dissipation specified in the absolute maximum ratings . the resistor-divider formed by the output resistor (r o ) and load impedance (r l ) scales the sampled voltage (v samp ). determine the output voltage (v out_ ) as follows: voltage gain = a v = r l / (r l + r o ) v out_ = v samp ? a v the maximum output voltage range depends on the ana-log supply voltages available and the scaling factor used: (v ss + 0.75v) ? a v v out_ (v dd - 2.4v) ? a v when rl = , then a v = 1, and this equation becomes: (v ss + 0.75v) v out (v dd - 2.4v) output clamp the max5167 clamps the output between two externallyapplied reference voltages. internal diodes connect all outputs to the clamping voltages, restricting the output voltage to: (v ch + 0.7v) v out_ (v cl - 0.7v) when the clamping voltage exceeds the maximum outputvoltage, the maximum output voltage will be the limiting factor. to disable output clamping, connect ch to v dd and cl to v ss to set the clamping voltages beyond the maximum output voltage range. the clamping diodesallow the max5167 to be used with other devices requiring restricted input voltages. timing definitions acquisition time (t aq ) is the time the max5167 must remain in sample mode for the hold capacitor toacquire an accurate sample. the hold-mode settling time (t h ) is the time necessary for the output voltage to settle to its final value. aperture delay (t ap ) is the time interval required to disconnect the input from the holdcapacitor. the hold pulse width (t pw ) is the time the max5167 must remain in hold mode while the addressis changed. data setup time (t ds ) is the time an address must be maintained at the digital input pinsbefore the address becomes valid. data hold time (t dh ) is the time an address must be maintained after thedevice is placed in hold mode ( figure 2 ). applications information multiplexing a dac figure 3 shows a typical demultiplexer application. different digital codes are converted by the digital-to-analog converter (dac) and then stored on 32 different channels of the max5167. the 40mv/s (max) droop rate requires refreshing the hold capacitors every 250ms before the voltage droops by 1/2lsb for an 8-bit dac with a 5v full-scale voltage. virtual 64 output sample and hold two max5167s can be configured to operate as a single64 output sample and hold. the upper and lower addressed devices are identified by config? logic level. connect the config pin of the upper device low, making its select pin active-high. connect the config pin of the lower device high to make the select pin active-low. figure 4 shows how to configure the devices. the devices now use only six address lines and a singles /h control to decode 64 outputs. address lines a0?4 from the control logic connect to addr0?ddr4 on 32-channel sample/hold amplifier with output clamping diodes 8 _______________________________________________________________________________________ downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes _______________________________________________________________________________________ 9 s/h addr_ select, config out_ in t pw t dh t h t ds t aq t ap hold step (channel x from hold to sample) (channel x from sample to hold) figure 2. timing diagram cs s/h select in out0out1 out30 out31 switches 0 31 address bus addr0 addr4 v l data bus config dac max5167 figure 3. multiplexing a dac downloaded from: http:///
max5167 both of the 32-channel devices. the a5 line toggles theselect pins of both devices to select the active one. the device that has config tied high responds to the lower 32 addresses (000000 through 011111). the device that has config grounded responds to the upper 32 addresses (100000 through 111111). input drive requirements the input of the max5167 feeds the inputs of 32 high-impedance buffers. these buffers are what charge the sample/hold capacitor through the multiplexer switch resistance. the bias current of a selected buffer is 10?, and this feeds into the 10pf input capacitance. figure 5 shows an equivalent input circuit. the bias cur- rents of the other 31 sample and holds are very small incomparison to the bias current of the selected channel. powering the max5167 the max5167 does not require a special power-upsequence to avoid latchup. the device requires three separate supply voltages for operation. however, when one or two of the voltages are not available, dc-dc charge-pump (switched-capacitor) converters provide a simple, efficient solution. the max860 provides volt- age doubling or inversion, ideal for conversions from +5v to +10v or from +5v to -5v. chip information transistor count: 6961 32-channel sample/hold amplifier with output clamping diodes 10 ______________________________________________________________________________________ out0out1 out30 out31 out32out33 out62 out63 max5167 max5167 config addr0 addr4 select s/h in config addr0 addr4 select s/h in a0 a4 a5wr input v l figure 4. 64 output sample-and-hold circuit i bias 10 a, i nh = low c in 10pf figure 5. input equivalent circuit downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes ______________________________________________________________________________________ 11 package information 32l/48l,tqfp.eps downloaded from: http:///
max5167 32-channel sample/hold amplifier with output clamping diodes maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes downloaded from: http:///

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